Generally, semiconductor devices may be divided into two categories: volatile semiconductor memory devices and non-volatile semiconductor memory devices. Volatile semiconductor memory devices, such as a dynamic random access memory (DRAM) device or a static random memory (SRAM) device, typically maintain data only when power is continuously supplied thereto, whereas non-volatile semiconductor memory devices, such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device or a flash memory device, may maintain data stored therein even when the power supply is interrupted or turned off. A ferroelectric random access memory (FRAM) device has characteristics similar to those of random access memory (RAM) devices, which are volatile memory devices and capable of both reading and writing, as well as characteristics of read-only memory (ROM) devices, which are non-volatile devices. Until now, the FRAM devices have had operation speeds relatively slower than those of the DRAM devices at least where the level of technology for manufacturing the FRAM devices has not advanced commensurate to that of the level of technology for manufacturing the DRAM devices. However, the FRAM devices generally possess desirable characteristics for storing data even when power is not supplied thereto at least because of spontaneous polarization characteristics. Accordingly, the FRAM devices may be useful for memory devices such as a calculator, which does not generally require high operation speeds, or a memory device for storing programs, in which data is not written frequently, yet storing data is important. Additionally, the FRAM devices may be operated with a power level lower than that of the EPROM devices or the EEPROM devices, and the number of inputs and outputs of the FRAM devices is generally larger than that of the EPROM devices or the EEPROM devices.
Ferroelectric materials that have been developed may include lead zirconate titanate (PZT or Pb(Zr, Ti)O3) and strontium bismuth tantalate (SBT or SrBi2Ta2O9). PZT may be manufactured by a plasma chemical vapor deposition (CVD) process and may have the advantage of possessing a large remnant polarization. However, a PZT layer may be highly fatigued when subjected to repeated polarization inversion. Additionally, PZT includes toxic lead (Pb). Alternatively, an SBT layer may not be readily fatigued when subjected to repeated polarization inversion, even when the polarization inversion is repeated more than approximately 1,000 times using a platinum (Pt) electrode, and the SBT layer may have an advantage of not having an imprint phenomenon of a polarization-voltage (P-V) hysteresis loop. However, the SBT layer is thermally treated at a high temperature over about 800° C. for crystallization.
A method of manufacturing the FRAM device including the above ferroelectrics is disclosed in Korean Laid-Open Patent Publication Nos. 2001-113271 and 2001-4306, and U.S. Pat. Nos. 6,351,006 and 6,194,228. When a PZT layer is formed on a substrate by a metal-organic CVD (MOCVD) process, a source gas for forming the PZT layer may be continuously provided, so that the PZT layer may have a rough surface. Thus, a FRAM device including the PZT layer may have poor electrical characteristics. More particularly, when the PZT layer is transferred so that an upper electrode may be formed thereon, remaining gases may be reacted with oxygen gas to form by-products having a large resistance on the PZT layer, and the PZT layer may have a rough surface. Accordingly, forming the upper electrode on the PZT layer may be complicated, and the upper electrode may be easily detached from the PZT layer. Additionally, reactive defects may be generated in a lower electrode by diffusion of the ferroelectric material in a deposition process, at least because the PZT layer is thermally treated at a temperature over about 650° C. for crystallization. The defects may deteriorate the electrical characteristics of the FRAM device.
An atomic layer deposition (ALD) process for forming a multi-element dielectric layer performed at a temperature under about 650° C. is disclosed in Korean Laid-Open Patent Publication No. 2006-3895, in an attempt to solve the above problems of the CVD process. According to the above-referenced publication, the ALD process includes a deposition process, a first purge process, an oxidation process and a second purge process in one cycle. When one cycle of the ALD process is performed, a vaporized mixed source is provided once. However, at least due to the characteristics of the ALD process, performing the ALD process requires a longer period of time than a CVD process, at least because two purge processes and an oxidation process are required in one cycle of the ALD process for depositing a layer. Additionally, developing source gases for forming a ferroelectric layer that are suitable for an ALD process is often met with difficulty.